module Mux(src1,src2,sel,out);

   input [31:0] src1, src2;
   input        sel;
   output       out;
   reg [31:0]   out;
   always @ (sel or src1 or src2)
     begin
        if (sel == 1'b1) begin
           out = src2;
        end else begin
           out = src1;
        end
     end

endmodule
